1. Field of the Invention
The present invention relates to a method for forming an isolation region of a semiconductor device, and more particularly, to a method for forming an isolation region of a semiconductor device with round active region edge corners when forming an isolation layer using a profiled groove isolation (PGI) trench structure.
2. Discussion of the Related Art
A number of methods are known for decreasing a size of a field oxide region (isolation region) for isolating semiconductor devices, and correspondingly increasing a size of an active region of the semiconductor devices. A local oxidation of silicon (LOCOS) method is often used to form the isolation region of a semiconductor device. This method is commonly used because of its simplicity and excellent reproducibility.
However, the LOCOS method forms a "bird's beak" at the field oxide layer's edge, which results in a decrease in the size of the active region of the semiconductor device. The "bird's beak" is a phenomenon where the field oxide layer encroaches on the active region. Therefore, the LOCOS method is not expected to be used for dynamic random access memory (DRAM) devices of 64 MB or more.
An advanced LOCOS method is employed for 64 MB or 256 MB DRAM devices that tries to prevent formation of the bird's beak or to remove the bird's beak entirely, in order to reduce the size of the isolation regions and increase the size of the active region.
However, the advanced LOCOS method has some disadvantages. Forming DRAM devices of 1 GB or more (requiring a cell region of 0.2 .mu.m.sup.2 and less) involves an increase in an area of the isolation region. A field oxide layer is formed on a surface of a silicon substrate, which in turn causes doping concentration in the silicon substrate to decrease, generating a leakage current, and degrading isolation region characteristics. Therefore, a different isolation region forming method for use in DRAM devices of 1 GB or more is being adopted to improve a thickness adjustment of the isolation region, and increase its isolating efficiency. This method involves formation of a trench.
A conventional method for forming a trench in an isolation region of a semiconductor device will be described below with reference to the attached drawings.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method for forming an isolation region of a semiconductor device.
As shown in FIG. 1A, a buffer oxide layer 2 and a nitride layer 3 are sequentially formed on a substrate 1.
As shown in FIG. 1B, a photoresist layer PR is coated on the nitride layer 3 to define an isolation region, and is patterned and selectively removed after an exposure and development processes. Subsequently, with the patterned photoresist layer PR serving as a mask, the nitride layer 3 and the buffer oxide layer 2 are sequentially etched, and then the substrate 1 is etched to form a trench 4.
The photoresist layer PR is removed, as shown in FIG. 1C. The surface of substrate 1 in the trench 4 is thermally treated to form a thermal oxide layer 5. A high density plasma (HDP) oxide layer 6 is then formed on an entire surface of nitride layer 3, including the thermal oxide layer 5 in the trench 4.
The formation of the thermal oxide layer 5 can prevent damage to the substrate 1 after the etching process that forms the trench 4. It can also relieve stress on the substrate 1 that is generated by a leakage current, or by an electric field concentration due to an angular shape of an upper corner "A" of a semiconductor device formed on the substrate 1.
As illustrated in FIG. 1D, the HDP oxide layer 6 and the nitride layer 3 are polished by a chemical mechanical polishing (CMP) method to form an isolation layer 6a at an upper portion of the trench 4.
The CMP process will be discussed below in detail. The HDP oxide layer 6 is polished to remain at the upper portion of the trench 4 of an isolation region. That is, when a top portion of the nitride layer 3 is exposed, the CMP process is stopped, removing the nitride layer 3. At this time, the nitride layer 3 is polished until a thickness of the nitride layer 3 becomes half of its previous thickness. Then the polishing process is stopped, and the nitride layer 3 is removed from the substrate 1.
As seen from FIG. ID, the sharply angular shape of upper corner "A" of the trench 4 is slightly rounded due to the thermal oxidation process.
The buffer oxide layer 2 is removed, as shown in FIG. 1E. The isolation layer 6a is also partially removed to be slightly higher than or level with the trench 4.
A gate oxide layer and a gate electrode (not shown) are then formed on the substrate 1 after the PGI formation process described above.
The conventional method for forming an isolation region of a semiconductor device has the following disadvantages.
First, formation of the thermal oxide layer cannot completely relieve the stress on the corner "A" of the trench 4, such as stress due to a leakage current or due to an electric field concentration, because of the angular shape of the upper corner "A" of the semiconductor device where the trench 4 is formed. Thus, formation of a reliable isolation region is only partially successful.
Second, the angular shape of upper corner "A" of the trench 4 may cause formation of voids in the trench 4, since the filling of the HDP oxide layer 6 is incomplete when an isolation layer is formed in the trench 4. This problem becomes more serious with more highly integrated semiconductor devices.